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GATE Questions of Computer Science 2014

Gate Questions for Computer Science likely to be asked for Gate 2014 is given here. Sample Questions given here will be helpful for all writing CS paper in Gate 2014. Model Question Papers with Answers for Computer Science have been prepared affter evaluating previous years questions in Gate.

COMPUTER SCIENCE  (CS) - GATE 2014 - SAMPLE QUESTIONS

 Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction 
(FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand 
(WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. 
There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A 
program consisting of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined processor. 
Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during 
the execution of this program, the time (in ns) needed to complete the program is
(A) 132 (B) 165 (C) 176 (D) 328 

A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders 
with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is 
(A) 4 (B) 5 (C) 6 (D) 7

Match the problem domains in GROUP I with the solution technologies in GROUP II. 
GROUP I GROUP II 
(P) Service oriented computing (1) Interoperability 
(Q) Heterogeneous communicating systems (2) BPMN
(R) Information representation (3) Publish-find-bind 
(S) Process description (4) XML 
(A) P-1, Q-2, R-3, S-4 (B) P-3, Q-4, R-2, S-1 
(C) P-3, Q-1, R-4, S-2 (D) P-4, Q-3, R-2, S-1 

The smallest integer that can be represented by an 8-bit number in 2’s complement form is 
(A) -256 (B) -128 (C) -127 (D) 0 


The following code segment is executed on a processor which allows only register operands in its 
instructions. Each instruction can have atmost two source operands and one destination operand. Assume 
that all variables are dead after this code segment. 
c = a + b; 
d = c * a; 
e = c + a; 
x = c * c; 
if (x > a) { 
y = a * a; 

else { 
d = d * d; 
e = e * e; 

Q.  Suppose the instruction set architecture of the processor has only two registers. The only allowed 
compiler optimization is code motion, which moves statements from one place to another while 
preserving correctness. What is the minimum number of spills to memory in the compiled code?
(A) 0 (B) 1 (C) 2 (D) 3 
Q.  What is the minimum number of registers needed in the instruction set architecture of the processor 
to compile this code segment without any spill to memory? Do not apply any optimization other 
than optimizing register allocation. 
(A) 3 (B) 4 (C) 5 (D) 6 

Related  Gate 2014
Download Syllabus for Gate 2014 Computer Science & Information Technology
Sample Question Papers for Computer Science & Information Technology - Gate 2014
Sample Question Papers for Computer Science - Gate 2014
GATE Examination Important Dates and Changes for 2014 Exams
Previous Question Papers (2013 Gate Exam)  Computer Science & Information Technology
Previous Question Papers (2012 Gate Exam) of Computer  Engineering
Previous Question Papers (2013 Gate Exam)  Computer Science
Previous Question Papers (2012 Gate Exam) of Information Technology
General Aptitude Questions for Computer Science & Information Technology
Seminar Topics  for Computer Science  Engineering