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GATE Questions of Computer Science and Information Technology 2014

Gate Questions for Computer Science & Information Technology likely to be asked for Gate 2014 is given here. Sample Questions given here will be helpful for all Information Technology students writing CS paper in Gate 2014. Model Question Papers with Answers for Information Technology have been prepared affter evaluating previous years questions jointly asked for Computer Science & Information Technology in Gate.

COMPUTER SCIENCE & INFORMATION TECHNOLOGY (CS) - GATE 2014 - SAMPLE QUESTIONS

 The procedure given below is required to find and replace certain characters inside an input character string supplied in array A. The characters to be replaced are supplied in array oldc, while their respective replacement characters are supplied in array newc. Array A has a fixed length of five characters, while arrays oldc and newc contain three characters each. However, the procedure is flawed. 
void find_and_replace (char *A, char *oldc, char *newc) { 
for (int i=0; i<5; i++) 
for (int j=0; j<3; j++) 
if (A[i] == oldc[j]) A[i] = newc[j]; 

The procedure is tested with the following four test cases. 
(1) oldc = “abc”, newc = “dab” (2) oldc = “cde”, newc = “bcd”
(3) oldc = “bca”, newc = “cda” (4) oldc = “abc”, newc = “bac”
Q. The tester now tests the program on all input strings of length five consisting of characters ‘a’, 
‘b’, ‘c’, ‘d’ and ‘e’ with duplicates allowed. If the tester carries out this testing with the four 
test cases given above, how many test cases will be able to capture the flaw?
(A) Only one (B) Only two (C) Only three (D) All four 
Q. If array A is made to hold the string “abcde”, which of the above four test cases will be successful 
in exposing the flaw in this procedure? 
(A) None (B) 2 only (C) 3 and 4 only (D) 4 only 

The smallest integer that can be represented by an 8-bit number in 2’s complement form is 
(A) -256 (B) -128 (C) -127 (D) 0 


A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table 
organization. The page table base register stores the base address of the first-level table (T1), which 
occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.
Q. What is the size of a page in KB in this computer? 
(A) 2 (B) 4 (C) 8 (D) 16 
Q. What is the minimum number of page colours needed to guarantee that no two synonyms map to 
different sets in the processor cache of this computer? 
(A) 2 (B) 4 (C) 8 (D) 16  

Related  Gate 2014
Download Syllabus for Gate 2014 Computer Science & Information Technology
Sample Question Papers for Computer Science & Information Technology - Gate 2014
Sample Question Papers for Computer Science - Gate 2014
GATE Examination Important Dates and Changes for 2014 Exams
Previous Question Papers (2013 Gate Exam)  Computer Science & Information Technology
Previous Question Papers (2012 Gate Exam) of Computer  Engineering
Previous Question Papers (2013 Gate Exam)  Computer Science
Previous Question Papers (2012 Gate Exam) of Information Technology
General Aptitude Questions for Computer Science & Information Technology
Seminar Topics  for Computer Science  Engineering