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Data rendition flip-flops for power down applications
On chip ESD protection sgategics for RF circuits in CMOS technologies
Trend and challenge on SOC design
An anti harmonic programmable DLL-based Frequency multiplier for dynamic frequency scaling
Intrusion aware SOC design which uncertainty classifications
Bio chip future basis for DNA computers
Master-Slave TNR inspired technique for fault tolerance at SRAM based FPGA
Low cost MIMO testing for RF integrated circuits
Design and comparison of Low power and high speed 4-bit ALU
Simulation of power grid networks considering wires and lognormal leakage current variations
temperature control frame work using wireless sensor networks and acoustical analysis for total special awareness
Memory less pipeline dynamic circuit design technique
Compressive acquisition CMOS image sensor from the algorithm to hardware implementation
Decoding in analog VLSI
The improved data encryption standard(DES) algorithm
A new VLSI architecture of parallel multiplier – accumulator based on radix to modified booth algorithm
Highly Parallel FPGA emulation for LPDC error floor characterization in perpendicular magnetic recording channel
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